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VirtuES: Embedded Multicore Systems Using Virtual Machine Approach

VirtuES

Publications by the people in VirtuES

Unfortunately the search engine of the TUCS publication database is broken, and it can only display the publications of an individual person. TUCS webmaster has been notified of this, and he promised fix it as soon as possible.

Notice, that the publications are selected by author, and some might not be related to the VirtuES project.


Tero Säntti, Joonas Tyystjärvi and Juha Plosila. An Improved Hardware Acceleration Scheme for Java Method Calls. In Norchip 2010, Nov 2010.

Joonas Tyystjärvi, Tero Säntti and Juha Plosila. Efficient Bytecode Optimizations for a Multicore Java Co-Processor System. In 2010 12th Biennial Baltic Electronics Conference (BEC2010), Oct 2010.

Joonas Tyystjärvi, Tero Säntti and Juha Plosila. Heap Access Optimizations for a Hardware-Accelerated Java Virtual Machine. In 2010 International Symposium on System-on-Chip, Sep 2010.

Joonas Tyystjärvi, Tero Säntti and Juha Plosila. Parallel Performance Evaluation of a Multicore Java Co-Processor System. In DATE 2010 Workshop "Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications", Mar 2010.

Joonas Tyystjärvi, Tero Säntti and Juha Plosila. Efficient Execution of Switch Instructions on a Multicore Java Co-Processor System. In IEEE TECHPOS 2009, Dec 2009.

Tero Säntti. A Co-Processor Approach for Efficient Java Execution in Embedded Systems. PhD thesis, 2008. https://oa.doria.fi/handle/10024/42248.

Joonas Tyystjärvi, Tero Säntti and Juha Plosila. Instruction Set Enhancements for High-Performance Multicore Execution on the REALJava Platform. In NORCHIP 2008, Nov 2008.

Tero Säntti, Joonas Tyystjärvi and Juha Plosila. A Novel Hardware Acceleration Scheme for Java Method Calls. In ISCAS 2008, May 2008.

Tero Säntti, Joonas Tyystjärvi and Juha Plosila. Java Co-Processor for Embedded Systems. In Processor Design - System-On-Chip Computing for ASICs and FPGAs. Nurmi, Jari, editors. , chapter 13, pages 287-308. Springer, 2007.

Tero Säntti, Joonas Tyystjärvi and Juha Plosila. FPGA Prototype of the REALJava Co-Processor. In 2007 International Symposium on System-on-Chip, Nov 2007.

Tero Säntti and Juha Plosila. Instruction Folding and Real Time Flow Control for a Java Execution Unit. Technical Report 707, TUCS, 2005.

Tero Säntti and Juha Plosila. Instruction Folding for an Asynchronous Java Co-Processor. In 2005 International Symposium of System-on-Chip, Nov 2005.

Tero Säntti and Juha Plosila. Real Time Flow Control for an Advanced Java Co-Processor . In Proceeding of IEEE 23rd Norchip Conference , Nov 2005.

Tero Säntti and Juha Plosila. Architecture for an Advanced Java Co-Processor. In International Symposium on Signals, Circuits & Systems, ISSCS 2005, Jul 2005.

Tero Säntti and Juha Plosila. Internal Structure of an Enhanced Java Execution Engine. Technical Report 665, TUCS, Feb 2005.

Tero Säntti and Juha Plosila. Communication Scheme for an Advanced Java Co-Processor. In Proceedings of IEEE Norchip 2004, Nov 2004.