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RealJava: Low-Power Java Co-Processor with Improved Real Time Performance and Predictability


The programming language Javatm has recently attracted quite a lot of interest in the embedded market (specifically mobile phones). Compared to more traditional programming languages, Java provides a number of advantages including hardware independency ("write-once, run-anywhere"), design reuse, dynamic upgrade of products, and faster time-to-market. However, there are several problems that need to be solved. These include slow execution rates, excessive memory requirements, very high power consumption mainly because of the excessive memory usage, and unpredictable real-time performance. The approaches to increase execution speed, like Just-In-Time (JIT) compilation, increase the memory consumption and thus also power consumption. On the other hand, optimizing the Java virtual machine for small memory consumption typically decreases the speed. To solve this dilemma, the REAL-JAVA project focuses on designing an advanced self-timed Java accelerator core which has extremely low power consumption while providing sufficient performance for even the most demanding real-time telecommunication and multimedia applications. This work also includes development of novel memory architectures, software support, and an advanced multimedia processing engine for real-time Java acceleration.

The goal is that the accelerator core can be directly attached to any general-purpose processor core running some Java-intensive application software. Asynchronous self-timed circuit technology, where timing is based on local handshakes between circuit blocks instead of a global clock signal, provides a promising platform for obtaining a highly modular low-power and low-noise Java accelerator implementation. In larger perspective, our Java core is targeted for future power-critical highly parallel telecommunication and multimedia single-chip systems built on self-timed network-like communication platforms with largely distributed control. These globally-asynchronous locally-synchronous (GALS) networks-on-chip (NoC) will be composed of hundreds of Intellectual Property (IP) blocks such as different processor cores, including a number of Java accelerator cores, on-chip memories, reconfigurable logic modules, application-specific blocks, and mixed-signal interface units. Adopting a self-timed handshake-based implementation for inter-module communication significantly improves design modularity, composability, and reliability restricting clock-related timing problems to relatively small locally synchronous islands. Furthermore, such asynchronous interfacing enables flexible use of stoppable local clocks providing automatic power down of idle system modules.

Work packages

The research in the REAL-JAVA project will be divided into four work packages: (1) design and implementation of an advanced self-timed Java accelerator core, (2) development of novel low-power memory circuits and architectures especially aimed for efficient Java processing, (3) software support development for Java acceleration, and (4) development of a reconfigurable Java-based single-chip multimedia processing engine architecture which will eventually serve as a substantial network-on-chip case study for the other work packages. The work is a joint effort of researchers from University of Turku (UTU) and ┼bo Akademi University (┼AU). The goal is to establish a strong internationally recognized research group in Turku around the implementation of Java for embedded and mobile platforms.

Current Status

The project is ending, and results can be found found here. The results show that the Java co-processor designed here provides very good performance, even better than any of the ASIC solutions. This is a remarkable achievement, considering that the REALJava runs on an FPGA and uses slower clock frequency than the fastest competitor. Clearly the approach is validated. Further research is carried out in the VirtuES project. That project is developing the multicore approach, considering both hardware and software aspects of the system.