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SeReNo: Service Based Reconfigurable NoC Architecture

Backgound

There is a widely accepted consensus in the processor design community that in the near future the number of cores, instead of processor clockrate, serves as the source of increase for processing power. Commercial chips available in 45 nm transistor technology accentuate this fact by allowing more devices to be integrated on a single chip and since 32 nm technology has already been demonstrated by several companies, and AMD, Freescale, IBM, STMicroelectronics, Toshiba and the College of Nanoscale Science and Engineering announced in last August that they jointly had developed and manufactured a working 22 nm SRAM cell, it is clear that the trend will continue. Although parallelism as a concept is about 40 years old, the literature is full of recent speculation and wondering on how to write multithreaded programs that efficiently use the resources of a multicore architecture. Also the decreasing feature sizes have increased device price of the ASICs. However FPGAs have not suffered such up pricing. Thus the FPGA domain is better suited for offering modern technologies to medium volume products. The trend is expected to continue, pushing the minimum viable volume for ASICs ever higher and opening new markets for FPGAs.

Motivation

There is a growing demand for solutions which allow the design of large and complex reconfigurable Systems-on-Chip (SoC) at high abstraction levels. The SeReNo project proposes a distributed service-based SoC architecture, i.e. a network of services offered by hardware cores or software processes. The architecture combines the flexible connectivity offered by a Network-on-Chip with a fully concurrent distributed SoC and through reconfiguration also allows better average hardware usage ratio. The proposed scheme offsets the negative aspects of using FPGAs, such as overheads in chip area, power consumption and execution rate, which have been charted in [1]. Firstly, the area overhead is reduced since not all of the hardware (HW) processing blocks are needed at the same time. This allows the system to selectively deploy only the blocks needed at any given time. Secondly, the power consumption overhead is reduced by the reconfigurable nature of the system, which allows for higher level of specialization in the execution blocks. ASICs also suffer from leakage currents even in the unused blocks and large clock trees required to span the whole chip. Both of these problems are almost entirely eliminated with the proposed techniques. Finally, the execution rate overhead is alleviated by the system allowing more efficient and application specific processing blocks. The cores can have several customizations tailored for given applications, while in traditional ASICs the cores tend to be quite general in order to keep them usable for a wider spectrum of applications. The reconfiguration also helps in shortening the design cycles and even more importantly in facilitating updates and upgrades in the field. Since FPGA chips are already tested by the manufacturer, the designs are simplified as they do not require any production testing logic. This further saves chip area, power and both design and execution time.

Objectives

The purpose of the SERENO project is (a) to create an efficient service based reconfigurable NoC architecture and (b) to develop understanding on how the platform should be programmed to fully utilize the potential of such a system. This understanding is reflected to the NoC architecture and service controller design as well as API based language constructs and program design methodology. With these components the performance of the system can be unleashed using easy and portable programming methods. The services provided by the system include processing blocks for accelerating the execution of platform agnostic user applications, such as Java applications using REALJava cores, audio and video codecs and 3D engines. Besides these, the SeReNo will provide system level support functions, like protocol processing engines, convolutional decoders (Viterbi), error correction, encryption and housekeeping. The flexibility of the system is increased with the possibility to implement some of the services as software modules, if hardware resources are not available.

Implementation

The research will be carried out using FPGA demonstration boards and design tools from Xilinx for the hardware components and Gnu cross compiling environment for the software components. These will be used to compose a complete embedded system with hardware and software components and also an operating system running on the background. As the operating system we are going to use Linux, which is widely used in embedded systems both in the research community and the industry as well. With this setup we can measure actual impact of using the proposed scheme in an embedded system and also find out the benefits of the improved programming models developed within this project. The project will focus on four main work packages. The first three will be executed one after another, while the fourth one is executed in parallel with the others. The work packages are: (1) creating a NoC architecture with support for multiple reconfigurable HW accelerators, (2) modifying the architecture to support service based addressing, (3) implementing mobile services that do not move data from a service to another, but rather move themselves to the data and (4) creating a large case study to be implemented on real hardware. The work packages are presented in more detail below, with a short summary of tasks at the end of each work package. The work packages are not assigned to any specific researcher, because active co-operation is required in each of them. More details on the distribution of the responsibilities can be found after the researcher presentations in Chapter 5.

Current Status

This project is in the preliminary study phase. Most of the work at moment is focusing setting the initial assumptions realistic. Also the work on the simulator model has started, and some research is being done on the dynamic reconfiguration facilites available on modern FPGA chips.