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UWI: Ultra Wideband Wireless Interconnects

Ultra Wideband Wireless Interconnects (UWI)

The goal of this research is to develop circuits and systems of RF transceiver for UWI applications to enable high data rate, low-power wireless communication for the new Network-on-Chip (NoC) application, either within a single chip or between multiple chips. There are a couple of steps in realization of this goal with each one must have the testing results except for T1:

T1. Transceiver System-Level Modeling & Simulation -- This task is to evaluate the effects on the performance of whole transceiver system caused by each building block under different physical environment and particular application, in order to provide detailed circuit specifications. The simulation can be carried on under both simulators depending on the schedule, and the validity of results might be compared and ensured. The documentation, as well as design review if needed, must be done after this task has completed. One or two papers about this job are to be submitted on international conferences.

T2. Wideband Power Amplifier Design -- In traditional PA design, there is a direct trade-off between linearity and efficiency which makes PA design difficult. It is particularly serious under sub-100nm CMOS technology. To overcome this problem, PA enhancement techniques must be explored. These techniques include efficiency and linearization enhancement such as pre-distortion, digital correction and automatic calibration etc. Surely, a fairly low cost in terms of silicon area and power consumption must be considered when use these methods. The documentation, as well as design review if needed, must be done after this task has completed. One or two papers about this job are to be submitted on international conferences or journals.

T3. Wideband Low-Noise Amplifier (LNA) Design -- It is the precondition for LNA design to retain good and uniform performance across the wideband frequency sprectrum. Under 90-nm or 65-nm process, ultra low power supply, substrate noise from digital circuits and parasitic effects become quite severe. Therefore, post-layout simulation and corner simulation must be done to guarantee that the LNA can work well after chip is tape-out. The documentation, as well as design review if needed, must be done after this task has completed. One or two papers about this job are to be submitted on international conferences.

T4. Wideband On-Chip Antenna Design -- As mentioned previously, the size of antenna should be optimized considering speed, bandwidth and impedance matching etc. Also the substrate noise model, channel model, package parasitics model and crosstalk between multi-chips might have to be established and simulated to validate the design. The documentation, as well as design review if needed, must be done after this task has completed. One or two papers about this job are to be submitted on international conferences.